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this is information on a product in full production. april 2013 docid024204 rev 2 1/32 32 LIS3MDL digital output magnetic sensor: ultra low-power, high performance 3-axis magnetometer datasheet - production data features ? wide supply voltage, 1.9 v to 3.6 v ? independent io supply (1.8 v) ? 4/ 8/ 12/ 16 gauss selectable magnetic full-scale ? continuous and single conversion mode ? 16-bit data output ? interrupt generator ? self-test ? i 2 c/spi digital output interface ? power-down mode/ low-power mode ? ecopack ? rohs and ?green? compliant applications ? magnetometer ? compass description the LIS3MDL is an ultra low-power high performance three axis magnetic sensor. the LIS3MDL has user selectable full-scales of 4/ 8/ 12/ 16 gauss. the self-test capability allows the user to check the functioning of the sensor in the final application. the device may be configured to generate interrupt signals for magnetic field detection. the LIS3MDL includes an i 2 c serial bus interface that supports standard and fast mode 100 khz and 400 khz and spi serial standard interface. the LIS3MDL is available in a small thin plastic land grid array package (lga) and is guaranteed to operate over an extended temperature range of -40 c to +85 c. lga-12 (2.0x2.0x1.0 mm) table 1. device summary order codes temperature range [ c] package packaging LIS3MDL -40 to +85 lga-12 tray LIS3MDLtr -40 to +85 lga-12 tape and reel www.st.com
contents LIS3MDL 2/32 docid024204 rev 2 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 magnetic and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 magnetic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4.2 sensor i2c - inter ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3 terminology and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 zero-gauss level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 high current wiring effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 i2c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.1 i2c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.3 spi read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
docid024204 rev 2 3/32 LIS3MDL contents 7 registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2 ctrl_reg1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3 ctrl_reg2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.4 ctrl_reg3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.5 ctrl_reg4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.6 ctrl_reg5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.7 status_reg (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.8 out_x_l (28h), out_x_h(29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.9 out_y_l (2ah), out_y_h (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.10 out_z_l (2ch), out_z_h (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.11 temp_out_l (2eh), temp_out_h (2fh) . . . . . . . . . . . . . . . . . . . . . . 27 7.12 int_cfg (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.13 int_src (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.14 int_ths_l(32h), int_ths_h(33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
list of tables LIS3MDL 4/32 docid024204 rev 2 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7. i2c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 9. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 10. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 11. sad+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 12. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 13. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 14. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 18 table 15. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 18 table 16. register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 17. who_am_i register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 18. ctrl_reg1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 19. ctrl_reg1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 20. x and y axes operating mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 21. output data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 22. ctrl_reg2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 23. ctrl_reg2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 24. full-scale selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 25. ctrl_reg3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 26. ctrl_reg3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 27. system operating mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 28. ctrl_reg4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 29. ctrl_reg4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 30. z-axis operating mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 31. ctrl_reg5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 32. ctrl_reg5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 33. status_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 34. status_reg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 35. int_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 36. int_cfg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 37. int_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 38. int_src description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 39. int_ths_l_m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 40. int_ths_h_m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 41. vflga 2x2x1 12ld pitch 0.5 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 42. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
docid024204 rev 2 5/32 LIS3MDL list of figures list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. spi slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. i2c slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. LIS3MDL electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. multiple bytes spi read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. multiple bytes spi write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. spi read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. vflga 2x2x1 12ld pitch 0.5 mm drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
block diagram and pin description LIS3MDL 6/32 docid024204 rev 2 1 block diagram and pin description 1.1 block diagram figure 1. block diagram 1.2 pin description figure 2. pin connection gams280120131409fsr i (m) y+ z+ y- z- x+ x- charge amplifier i2c spi cs scl/spc sda/sdi/sdo sdo/sa1 control logic clock trimming circuits a/d control converter mux logic interrupt generator gams280120131415fsr vdd_io c1 sc l/spc res gnd drdy vdd res cs bottom view 4 1 5 6 int 11 12 sda/sdi/sdo 7 10 sd0/sa1 top view direction of detectable magnetic fields x z y
docid024204 rev 2 7/32 LIS3MDL block diagram and pin description table 2. pin description pin# name function 1 scl spc i 2 c serial clock (scl) spi serial port clock (spc) 2 reserved connect to gnd 3 gnd connect to gnd 4 c1 capacitor connection (c1=100 nf) 5 vdd power supply 6 vdd_io power supply for i/o pins 7 int interrupt 8 drdy data ready 9 sdo sa1 spi serial data output (sdo) i 2 c less significant bit of the device address (sa1) 10 cs spi enable i 2 c/spi mode selection (1: spi idle mode / i2c communication enabled; 0: spi communication mode / i 2 c disabled) 11 sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 12 reserved connect to gnd
magnetic and electrical specifications LIS3MDL 8/32 docid024204 rev 2 2 magnetic and electrical specifications 2.1 magnetic characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted (a) a. the product is factory calibrated at 2.5 v. the operational power supply range is from 1.9 v to 3.6 v. table 3. mechanical characteristics symbol parameter test conditions min. typ. (1) max. unit fs measurement range 4 gauss 8 12 16 gn sensitivity fs=4 gauss 6842 lsb/ gauss fs=8 gauss 3421 fs=12 gauss 2281 fs=16 gauss 1711 zgauss zero-gauss level fs=4 gauss 1 gauss rms rms noise x-axis; fs=12 gauss; ultra-high performance mode 3.2 mgauss y-axis; fs=12 gauss ultra-high performance mode 3.2 mgauss z-axis; fs=12 gauss ultra-high performance mode 4.1 mgauss nl non-linearity best fit straight line fs=12 gauss happlied = 6 gauss 0.12 %fs st self test (2) x-axis fs = 12 gauss 13 gauss y-ax is fs = 12 gauss 13 z-axis fs = 12 gauss 0.1 1 df magnetic disturbing field zero-gauss offset starts to degrade 50 gauss to p operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. absolute value.
docid024204 rev 2 9/32 LIS3MDL magnetic and electrical specifications 2.2 temperature sensor characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted (b) . 2.3 electrical characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted (c) b. the product is factory calibrated at 2.5 v. table 4. temperature sensor characteristics symbol parameter test conditions min. typ. (1) max. unit tsdr temperature sensor output change vs. temperature - 8 lsb/c todr temperature refresh rate (2) odr hz top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. if temp_en bit in ctrl_reg1 (20h) is set to?1?, a temperature data is ac quired at each conversion cycle. refer to ta b le 2 1 c. the product is factory calibrated at 2.5 v. the operational power supply range is from 1.9 v to 3.6 v. table 5. electrical characteristics symbol parameter test conditions min. typ. (1) max. unit vdd supply voltage 1.9 3.6 v vdd_io power supply for i/o 1.71 1.8 vdd+0.1 idd_hr current consumption in ultra-high resolution mode odr = 20 hz 270 a idd_lp current consumption in low-power mode odr = 20 hz 40 a idd_pd current consumption in power down 1 a top operating temperature range -40 +85 c 1. typical specification are not guaranteed.
magnetic and electrical specifications LIS3MDL 10/32 docid024204 rev 2 2.4 communication interface characteristics 2.4.1 spi - serial peripheral interface subject to general operating conditions for vdd and top. figure 3. spi slave timing diagram (d) table 6. spi slave timing values symbol parameter value (1) 1. values are guaranteed at 10 mhz clock frequency for spi with both 4 and 3 wires, based on characterization results, not tested in production. unit min. max. tc(spc) spi clock cycle 100 ns fc(spc) spi clock frequency 10 mhz tsu(cs) cs setup time 5 ns th(cs) cs hold time 20 tsu(si) sdi input setup time 5 th(si) sdi input hold time 15 tv(so) sdo valid output time 50 th(so) sdo output hold time 5 tdis(so) sdo output disable time 50 d. measurement points are done at 0.2? vdd_io and 0.8? vdd_io, for both input and output ports. spc cs sdi sdo t su(cs) t v(so) t h(so) t h(si) t su(si) t h(cs) t dis(so) t c(spc) msb in msb out lsb out lsb in
docid024204 rev 2 11/32 LIS3MDL magnetic and electrical specifications 2.4.2 sensor i 2 c - inter ic control interface subject to general operating conditions for vdd and top. figure 4. i 2 c slave timing diagram (e) table 7. i 2 c slave timing values symbol parameter i 2 c standard mode (1) i 2 c fast mode (1) unit min. max. min. max. f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 3.45 0 0.9 s t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b (2) 300 ns t f(sda) t f(scl) sda and scl fall time 300 20 + 0.1c b (2) 300 t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement, not tested in production. 2. cb = total capacitance of one bus line, in pf. e. measurement points are done at 0.2? vdd_io and 0.8? vdd_io, for both ports. 6'$ 6&/ w i6'$ w vx63 w z6&// w vx6'$ w u6'$ w vx65 w k67 w z6&/+ w k6'$ w u6&/ w i6&/ w z6365 67$57 5(3($7(' 67$57 6723 67$57
magnetic and electrical specifications LIS3MDL 12/32 docid024204 rev 2 2.5 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 4.8 v. table 8. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 4.8 v vdd_io i/o pins supply voltage -0.3 to 4.8 v vin input voltage on any control pin (scl/spc, sda/sdi/sdo, sdo/sa1, cs) -0.3 to vdd_io +0.3 v a unp acceleration (any axis) 3,000 for 0.5 ms g 10,000 for 0.1 ms g m ef maximum exposed field 1000 gauss t op operating temperature range -40 to +85 c t stg storage temperature range -40 to +125 c this is a device sensitive to magnetic fields, improper handling can cause permanent damage to the part this is an esd sensitive device, improper handling can cause permanent damage to the part
docid024204 rev 2 13/32 LIS3MDL terminology and functionality 3 terminology and functionality 3.1 sensitivity sensitivity describes the gain of the sensor and can be determined, for example, by applying a magnetic field of 1 gauss to it. 3.2 zero- gauss level zero- g auss level offset describes the deviation of an actual output signal from the ideal output if no magnetic field is present. 3.3 factory calibration the ic interface is factory calibrated for sensitivity (so) and zero- gauss level (tyoff). the trimming values are stored in the device in non-volatile memory. each time the device is turned on, the trimming parameters are downloaded to the registers to be used during active operation. this allows the device to be used without further calibration.
application hints LIS3MDL 14/32 docid024204 rev 2 4 application hints figure 5. LIS3MDL electrical connections 4.1 external capacitors the LIS3MDL requires one external capacitor (c1=100 nf) connected between pin 4 and gnd. the device core power supply line (vdd) needs one high frequency decoupling capacitor (c3=100 nf, ceramic) as near as possible to the supply pin, and a low frequency electrolytic capacitor (c2=1 f) . all the voltage and ground supplies must be present at the same time to have proper behavior of the ic (refer to figure 5 ). the functionality of the device and the measured magnetic field data is selectable and accessible through the i 2 c / spi interfaces. the functions, the threshold and the timing of the interrupt pin (int) can be completely programmed by the user through the i 2 c / spi interfaces. when i 2 c or 3-wire spi is used the sdo/sa1 pin must be connected to vdd_io or gnd. 4.2 soldering information the lga package is compliant with the ecopack ? , rohs and ?green? standard. it is qualified for soldering heat resistance according to jedec j-std-020. land pattern and soldering recommendations are available at www.st.com . gams280120131435fsr vdd c 3 =100 nf gnd sda/sdi/sdo scl/spc c 2 =1 f 4 1 5 5 7 7 11 12 vdd_io cs c 1 =100 nf (top view) 10 sdo/sa1 drdy 8 int 6 9 2 3 top view direction of detectable magnetic fields x z y
docid024204 rev 2 15/32 LIS3MDL application hints 4.3 high current wiring effects high current in wiring and printed circuit traces can cause errors in magnetic field measurements for compassing. conductor-generated magnetic fields will add to the earth?s magnetic field, causing errors in compass heading computation. keep currents higher than 10 ma a few millimeters further away from the sensor ic.
digital interfaces LIS3MDL 16/32 docid024204 rev 2 5 digital interfaces the registers embedded in the LIS3MDL may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode. the serial interfaces are mapped onto the same pads. to select/exploit the i 2 c interface, the cs line must be tied high (i.e. connected to vdd_io). 5.1 i 2 c serial interface the LIS3MDL i 2 c is a bus slave. the i 2 c is employed to write data to registers whose content can also be read back. the relevant i 2 c terminology is given in the table below. there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. both lines must be connected to vdd_io through an external pull-up resistor. when the bus is free, both the lines are high. the i 2 c interface is compliant with fast mode (400 khz) i 2 c standards, as well as with normal mode. when the i 2 c interface is used, the sdo/sa1 pin has to be connected to vdd_io or gnd. table 9. serial interface pin description pin name pin description cs spi enable i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) scl spc i 2 c serial clock (scl) spi serial port clock (spc) sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sa1 sdo i 2 c less significant bit of the device address (sa1) spi serial data output (sdo) table 10. serial interface pin description term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
docid024204 rev 2 17/32 LIS3MDL digital interfaces 5.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high to low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first seven bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the save address (sad) associated to the LIS3MDL is 00111x0b, whereas the x bit is modified by the sdo/sa1 pin in order to modify the device address. if the sdo/sa1 pin is connected to the voltage supply, the address is 00 11110b, otherwise, if the sdo/sa1 pin is connected to ground, the address is 0011100b. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded inside the LIS3MDL behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent, once a slave acknowledge (sak) has been returned, an 8-bit sub-address (sub) is transmitted: the 7 lsb represent the actual register address while the msb enables address auto-increment. if the msb of the sub field is ?1?, the sub (register address) is automatically increased to allow multiple data read/write. the slave address is completed with a read/write bit. if the bit was ?1? (read), a repeated start (sr) condition must be issued after the two sub-address bytes; if the bit is ?0? (write) the master will transmit to the slave with direction unchanged. tab le 11 explains how the sad+read/write bit pattern is composed, listing all the possible configurations. table 11. sad+read/write patterns command sad[6:2] sad[1] = sdo/sa1 sad[0] r/w sad+r/w read 00111 0 0 1 00111001 (39h) write 00111 0 0 0 00111000 (38h) read 00111 1 0 1 00111101 (3dh) write 00111 1 0 0 00111100 (3ch) table 12. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak
digital interfaces LIS3MDL 18/32 docid024204 rev 2 data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver cannot receive another complete byte of data until it has performed some other function, it can hold the clock line scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver does not acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. in other words, sub(7) must be equal to 1, while sub(6-0) represents the address of first register to be read. in the presented communication format, mak is master acknowledge and nmak is no master acknowledge. 5.2 spi bus interface the LIS3MDL spi is a bus slave. the spi allows writing and reading the registers of the device. the serial interface interacts with the outside world through 4 wires: cs , spc , sdi and sdo . table 13. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak table 14. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 15. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data dat a data
docid024204 rev 2 19/32 LIS3MDL digital interfaces figure 6. read and write protocol cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port data input and output. those lines are driven at the falling edge of spc and should be captured at the rising edge of spc . both the read register and write register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple bytes read/write. bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc just before the rising edge of cs . bit 0 : rw bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in latter case, the chip will drive sdo at the start of bit 8. bit 1 : ms bit. when 0, the address will remain unchanged in multiple read/write commands. when 1, the address is auto-incremented in multiple read/write commands. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written into the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). in multiple read/write commands further blocks of 8 clock periods will be added. when ms bit is ?0? the address used to read/write data remains the same for every block. when ms bit is ?1? the address used to read/write data is increased at every block. the function and the behavior of sdi and sdo remain unchanged. cs spc sdi sdo rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 do7do6do5do4do3do2do1do0 ms am10129v1
digital interfaces LIS3MDL 20/32 docid024204 rev 2 5.2.1 spi read figure 7. spi read protocol the spi read command is performed with 16 clock pulses. multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that will be read from the device (msb first). bit 16-... : data do(...-8). further data in multiple byte reading. figure 8. multiple bytes spi read protocol (2 bytes example) cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms am10130v1 cs sp c sdi sd o rw do7do6do5do4do3do2 do1do0 ad5 ad4 ad 3 ad2 ad1 ad0 do 15 do 14 do 13 do 12 do 11 do 10 d o9 d o8 ms am10131v1
docid024204 rev 2 21/32 LIS3MDL digital interfaces 5.2.2 spi write figure 9. spi write protocol the spi write command is performed with 16 clock pulses. multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : write bit. the value is 0. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written inside the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writing. figure 10. multiple bytes spi write protocol (2 bytes example) 5.2.3 spi read in 3-wire mode 3-wire mode is entered by setting to ?1? bit sim (spi serial interface mode selection) in ctrl_reg3 (22h) . when 3-wire mode is used the sdo/sa1 pin has to be connected to gnd or vdd_io. cs spc sdi rw di7di6di5di4di3di2di1di0 ad5 ad 4 ad 3 ad2 ad 1 ad0 ms am10132v1 cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad 0 di 7 d i6 di 5 d i4 di 3 di 2 di 1 di 0 di 15 d i1 4 di 13 d i1 2 di 11 di 10 di 9 di 8 ms am10133v1
digital interfaces LIS3MDL 22/32 docid024204 rev 2 figure 11. spi read protocol in 3-wire mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). multiple read command is also available in 3-wire mode. cs spc sdi/o rw do7do6do5do4do3do2do1do0 ad5 ad 4 ad 3 ad2 ad1 ad 0 ms am10134v1
docid024204 rev 2 23/32 LIS3MDL register mapping 6 register mapping the table below provides a list of the 8-bit registers embedded in the device and their respective addresses: registers marked reserved or not listed in the table above must not be changed. writing to those registers may cause permanent damage to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered up. table 16. register address map name type register address default comment hex binary reserved 00 - 0e -- -- reserved who_am_i r 0f 0000 1111 00111101 dummy register reserved 10 - 1f -- -- reserved ctrl_reg1 r/w 20 0010 0000 00010000 ctrl_reg2 r/w 21 0010 0001 00000000 ctrl_reg3 r/w 22 0010 0010 00000011 ctrl_reg4 r/w 23 0010 0011 00000000 ctrl_reg5 r/w 24 0010 0100 00000000 reserved 25 - 26 -- -- reserved status_reg r 27 0010 0111 output out_x_l r 28 0010 1000 output out_x_h r 29 0010 1001 output out_y_l r 2a 0010 1010 output out_y_h r 2b 0010 1011 output out_z_l r 2c 0010 1100 output out_z_h r 2d 0010 1101 output reserved 2e - 2f -- -- reserved status_reg rw 30 00110000 00000000 int_src r 31 00110001 00000000 int_ths_l r 32 00110010 00000000 int_ths_h r 33 00110011 00000000
registers description LIS3MDL 24/32 docid024204 rev 2 7 registers description 7.1 who_am_i (0fh) device identification register. 7.2 ctrl_reg1 (20h) table 17. who_am_i register 00111101 table 18. ctrl_reg1 register temp_en om1 om0 do2 do1 do0 0 (1) 1. this bit must be set to ?0? for correct functioning of the device st table 19. ctrl_reg1 description temp_en temperature sensor enable. default value: 0 (0: temperature sensor disabled; 1: temperature sensor enabled) om[1:0] x and y axes operative mode selection. default value: 00 (refer to table 20 ) do[2:0] output data rate selection. default value: 100 (refer to table 21 ) st self-test enable. default value: 0 (0: self-test disabled; 1: self-test enabled) table 20. x and y axes operating mode selection om1 om0 operating mode for x and y axes 0 0 low-power mode 0 1 medium performance mode 1 0 high performance mode 1 1 ultra-high performance mode table 21. output data rate configuration do2 do1 do0 odr [hz] 0000.625 0011.25
docid024204 rev 2 25/32 LIS3MDL registers description 7.3 ctrl_reg2 (21h) 7.4 ctrl_reg3 (22h) 0102.5 0115 10010 10120 11040 11180 table 21. output data rate configuration (continued) do2 do1 do0 odr [hz] table 22. ctrl_reg2 register 0 (1) 1. these bits must be set to ?0? for correct functioning of the device fs1 fs0 0 (1) reboot soft_rst 0 (1) 0 (1) table 23. ctrl_reg2 description fs[1:0] full-scale configuration. default value: 00 refer to table 24 reboot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content) soft_rst configuration registers and user register reset function. (0: default value; 1: reset operation) table 24. full-scale selection fs1 fs0 full-scale 0 0 4 gauss 0 1 8 gauss 1 0 12 gauss 1 1 16 gauss table 25. ctrl_reg3 register 0 (1) 1. these bits must be set to ?0? for correct functioning of the device 0 (1) lp 0 (1) 0 (1) sim md1 md0
registers description LIS3MDL 26/32 docid024204 rev 2 7.5 ctrl_reg4 (23h) table 26. ctrl_reg3 description lp low-power mode configuration. default value: 0 if this bit is ?1?, the do[2:0] is set to 0.625 hz and the system performs, for each channel, the minimum number of averages. once the bit is set to ?0?, the magnetic data rate is configured by do bits in ctrl_reg1 (20h) register. sim spi serial interface mode selection. default value: 0 (0: 4-wire interface; 1: 3-wire interface). md[1:0] operating mode selection. default value: 11 refer to table : table 27. system operating mode selection md1 md0 mode 0 0 continuous-conversion mode 0 1 single-conversion mode single-conversion mode has to be used with sampling frequency from 0.625hz to 80hz. 1 0 power-down mode 1 1 power-down mode table 28. ctrl_reg4 register 0 (1) 1. these bits must be set to ?0? for correct functioning of the device 0 (1) 0 (1) 0 (1) omz1 omz0 ble 0 (1) table 29. ctrl_reg4 description omz[1:0] z-axis operative mode selection. default value: 00. refer to table 30 ble big/little endian data selection. default value: 0 (0: data lsb at lower address; 1: data msb at lower address) table 30. z-axis operating mode selection omz1 omz0 operating mode for z-axis 0 0 low-power mode 0 1 medium performance mode 1 0 high performance mode 1 1 ultra-high performance mode
docid024204 rev 2 27/32 LIS3MDL registers description 7.6 ctrl_reg5 (24h) 7.7 status_reg (27h) table 31. ctrl_reg5 register 0 (1) 1. these bits must be set to ?0? for correct functioning of the device bdu 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) table 32. ctrl_reg5 description bdu block data update for magnetic data. default value: 0 (0: continuous update; 1: output registers not updated until msb and lsb have been read) table 33. status_reg register zyxor zor yor xor zyxda zda yda xda table 34. status_reg description zyxor x, y and z axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new set of data has overwritten the previous one) zor z axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the z-axis has overwritten the previous data) yor y axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the y-axis has overwritten the previous data) xor x axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the x-axis has overwritten the previous data) zyxda x, y and z axis new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) zda z axis new data available. default value: 0 (0: a new data for the z-axis is not yet available; 1: new data for the z-axis is available) yda y axis new data available. default value: 0 (0: a new data for the y-axis is not yet available; 1: new data for the y-axis is available) xda x axis new data available. default value: 0 (0: a new data for the x-axis is not yet available; 1: new data for the x-axis is available)
registers description LIS3MDL 28/32 docid024204 rev 2 7.8 out_x_l (28h), out_x_h(29h) x-axis data output. the value of magnetic field is expressed as two?s complement. 7.9 out_y_l (2ah), out_y_h (2bh) y-axis data output. the value of magnetic field is expressed as two?s complement. 7.10 out_z_l (2ch), out_z_h (2dh) z-axis data output. the value of magnetic field is expressed as two?s complement. 7.11 temp_out_l (2eh), temp_out_h (2fh) temperature sensor data. the value of temperature is expressed as two?s complement. 7.12 int_cfg (30h) table 35. int_cfg register xien yien zien 0 (1) 1. these bits must be set to ?0? for correct functioning of the device 0 (1) iea lir ien table 36. int_cfg description xien enable interrupt generation on x axis. default value: 0 0: disable interrupt request; 1: enable interrupt request yien enable interrupt generation on y axis. default value: 0 0: disable interrupt request; 1: enable interrupt request zien enable interrupt generation on z axis. default value: 0 0: disable interrupt request; 1: enable interrupt request iea interrupt active configuration on int. default value 0 0: low; 1:high lir latch interrupt request. default value: 0 0: interrupt request latched; 1: interrupt request not latched) once latched, int pin remains in the same state until int_src(31h) is read. ien interrupt enable on int pin. default value 0. 0: disable; 1: enable
docid024204 rev 2 29/32 LIS3MDL registers description 7.13 int_src (31h) 7.14 int_ths_l(32h), int_ths_h(33h) interrupt threshold. default value: 0. the value is expressed in 16-bit unsigned. even if the threshold is expressed in absolute value, the device detects both positive and negative thresholds. table 37. int_src register pth_x pth_y pth_z nth_x nth_y nth_z mroi int table 38. int_src description pth_x value on x-axis exceeds the threshold on the positive side. default value: 0. pth_y value on y-axis exceeds the threshold on the positive side. default value: 0. pth_z value on z-axis exceeds the threshold on the positive side. default value: 0. nth_x value on x-axis exceeds the threshold on the negative side. default value: 0. nth_y value on y-axis exceeds the threshold on the negative side. default value: 0. nth_z value on z-axis exceeds the threshold on the negative side. default value: 0. mroi internal measurement range overflow on magnetic value. default value: 0. int this bit signals when interrupt event occours. table 39. int_ths_l_m ths7 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 40. int_ths_h_m 0 (1) 1. these bits must be set to ?0? for correct functioning of the device ths14 ths13 ths12 ths11 ths10 ths9 ths8
package information LIS3MDL 30/32 docid024204 rev 2 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark. figure 12. vflga 2x2x1 12ld pitch 0.5 mm drawing table 41. vflga 2x2x1 12ld pitch 0.5 mm mechanical data dim. mm min. typ. max. a1 1 a2 0.785 a3 0.200 d1 1.850 2.000 2.150 e1 1.850 2.000 2.150 l1 1.500 n1 0.500 t1 0.275 t2 0.250 p2 0.075 r 45 m0.100 k0.050 8365767_a
docid024204 rev 2 31/32 LIS3MDL revision history 9 revision history table 42. document revision history date revision changes 01-feb-2013 1 first release. 22-apr-2013 2 updated note on page 12 products status changed from preliminary data to production data.
LIS3MDL 32/32 docid024204 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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